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? semiconductor components industries, llc, 2016 july, 2016 ? rev. 0 1 publication order number: ncp81239/d ncp81239 usb power delivery 4-switch buck boost controller the ncp81239 usb power delivery (pd) controller is a synchronous buck boost that is optimized for converting battery voltage or adaptor voltage into power supply rails required in notebook, tablet, and desktop systems, as well as many other consumer devices using usb pd standard and c ? type cables. the ncp81239 is fully compliant to the usb power delivery specification when used in conjunction with a usb pd or c ? type interface controller. ncp81239 is designed for applications requiring dynamically controlled slew rate limited output voltage that require either voltage higher or lower than the input voltage. the ncp81239 drives 4 nmosfet switches, allowing it to buck or boost and support the consumer and provider role swap function specified in the usb power delivery specification which is suitable for all usb pd applications. the usb pd buck boost controller operates with a supply and load range of 4.5 v to 28 v. features ? wide input voltage range: from 4.5 v to 28 v ? dynamically programmed frequency from 150 khz to 1.2 mhz ? i 2 c interface ? real time power good indication ? controlled slew rate voltage transitioning ? feedback pin with internally programmed reference ? support usbpd/qc2.0/qc3.0 profile ? 2 independent current sensing inputs ? over temperature protection ? adaptive non ? overlap gate drivers ? filter capacitor switch control ? over ? voltage and over ? current protection ? dead battery power support ? 5 x 5 mm qfn32 package typical application ? notebooks, tablets, desktops ? all in ones ? monitors, tvs, and set top boxes ? consumer electronics www.onsemi.com ordering information device package shipping ? NCP81239MNTXG qfn32 (pb ? free) 4000 / tape & reel qfn32 5x5, 0.5p case 485ce marking diagram ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. ncp81239 awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package (note: microdot may be in either location) 32 1
ncp81239 www.onsemi.com 2 figure 1. typical application circuit cs1 cs2 clind sda scl vdrv int flag i2c curret limit indicator interrupt v1 v2 hsg1 hsg2 bst2 lsg1 lsg2 csp1 fb vsw1 vsw2 bst1 csn1 csp2 cfet1 comp pgnd1 pgnd2 agnd q1 q2 q3 q4 cb1 cb2 cp cc rc co2 q5 enable vcc dbin 5v rail en pdrv c vcc c vdrv dbout co1 q6 rpu rpd r cs1 r cs2 r drv rs2 rs1 l1 dead battery / vconn current sense 1 current sense 2 csn2 v1 figure 2. pinout 17 18 19 20 21 22 23 24 15 14 13 12 11 10 9 16 hsg2 lsg2 csn2 csp2 fb cs2 pgnd2 pdrv en comp int sda scl agnd agnd cfet 1 2 3 4 5 6 7 8 hsg1 lsg1 csp1 csn1 v1 pgnd1 clind cs1 31 30 29 28 27 26 25 32 dbout vsw2 vsw1 bst2 bst1 vdrv vcc dbin
ncp81239 www.onsemi.com 3 figure 3. block diagram startup input uvlo _ + _ + ? + error ota 500 s /100 s co2 bst1 hsg1 vsw1 lsg1 vdrv pgnd1 lsg2 vdrv pgnd2 bst2 hsg2 vsw2 nol drive logic_2 nol drive logic_1 csn1 csp1 v1 + _ csp2 csn2 vcc vdrv cs1 cs2 cs1 cs1 cs2 cs2 nc clind int sda scl limit registers status registers i2c interface digital configuration oscillator reference int interface vfb comp ? + cc rc cp cs2_int cs2_int cs1_int cs1_int 0_ramp buck logic boost logic buck boost logic config config sw1 sw2 sw3 sw4 vdrv cfet dbin current limiting circuit for dead battery config vfb pg thermal shutdown ts control logic sw1 sw2 sw3 sw4 iuvlob bg iuvlob pg ts clind bg + ? clindp1 climp1 ? + en 0.8v en en ts ? + cl2p cl2p ref cs2_int cl2 cl1 bg value register adc csp1 cs1_int cs2_int analog mux agnd flag + ? clindp2 climp2 clind vcc en logic enpol en_mask ? + vfb pg_low pg_high ? + pg vfb pg_msk ov_ref ov pg/ ov/ logic ov_msk ? + co vdrv + ? cl2n ref cl2n config config ? + cl1p cl1p ref cs1_int + ? cl1n ref cl1n config cs1_int 0_ramp vdrv pdrv cfet pdrv q2 v1 + ? 4.0v vdrv_rdy + ? 4.0v vcc_rdy + boot1v boot1 _uvlo + boot1v boot2 _uvlo q1 v2 dbout v1 fb 180_ramp ramp_0 ramp_180 csp1 csn2 vfb pdrv cfet table 1. pin function description pin pin name description 1 hsg1 s1 gate drive. drives the s1 n ? channel mosfet with a voltage equal to vdrv superimposed on the switch node voltage vsw1. 2 lsg1 drives the gate of the s2 n ? channel mosfet between ground and vdrv. 3, 22 pgnd power ground for the low side mosfet drivers. connect these pins closely to the source of the bottom n ? channel mosfets. 4 csn1 negative terminal of the current sense amplifier. 5 csp1 positive terminal of the current sense amplifier. 6 v1 input voltage of the converter 7 cs1 current sense amplifier output. cs1 will source a current that is proportional to the voltage across rs1 to an external resistor. ground this pin if not used. 8 clind open drain output to indicate that the cs1 or cs2 voltage has exceeded the i 2 c programmed limit. 9 sda i 2 c interface data line. 10 scl i 2 c interface clock line. 11 int interrupt is an open drain output that indicates the state of the output power, the internal thermal trip, and oth- er i 2 c programmable functions. 12 cfet controlled drive of an external mosfet that connects a bulk output capacitor to the output of the power converter. necessary to adhere to low capacitance limits of the standard usb specifications for power prior to usb pd negotiation. 13 ? 14 agnd the ground pin for the analog circuitry. 15 comp output of the transconductance amplifier used for stability in closed loop operation.
ncp81239 www.onsemi.com 4 table 1. pin function description pin description pin name 16 en precision enable starts the part and places it into default configuration when toggled. 17 pdrv the open drain output used to control a pmosfet. 18 cs2 current sense amplifier output. cs2 will source a current that is proportional to the voltage across rs2 to an external resistor. ground this pin if not used. 19 fb feedback voltage of the output, negative terminal of the gm amplifier. 20 csn2 negative terminal of the current sense amplifier. 21 csp2 positive terminal of the current sense amplifier. 23 lsg2 drives the gate of the s2 n ? channel mosfet between ground and vdrv. 24 hsg2 s4 gate drive. drives the s4 n ? channel mosfet with a voltage equal to vdrv superimposed on the switch node voltage vsw2. 25 bst2 bootstrapped driver supply. the bst2 pin swings from a diode voltage below vdrv up to a diode voltage below fb + vdrv. place a 0.1 f capacitor from this pin to vsw2. 26 vsw2 switch node. vsw2 pin swings from a diode voltage drop below ground up to output voltage. 27 dbout the output of the dead battery circuit which can also be used for the vconn voltage supply. 28 dbin the dead battery input to the converter where 5 v is applied. a 1 f capacitor should be placed close to the part to decouple this line. 29 vdrv internal voltage supply to the driver circuits. a 1 f capacitor should be placed close to the part to decouple this line. 30 vcc the vcc pin supplies power to the internal circuitry. the vcc is the output of a linear regulator which is pow- ered from v1. can be used to supply up to a 100 ma load. pin should be decoupled with a 1 f capacitor for stable operation. 31 vsw1 switch node. vsw1 pin swings from a diode voltage drop below ground up to v1. 32 bst1 driver supply. the bst1 pin swings from a diode voltage below vdrv up to a diode voltage below v1 + vdrv. place a 0.1 f capacitor from this pin to vsw1. 33 thpad center thermal pad. connect to agnd externally. table 2. maximum ratings over operating free ? air temperature range unless otherwise noted rating symbol min max unit input of the dead battery circuit dbin ? 0.3 5.5 v output of the dead battery circuit dbout ? 0.3 5.5 v driver input voltage vdrv ? 0.3 5.5 v internal regulator output vcc ? 0.3 5.5 v output of current sense amplifiers cs1, cs2 ? 0.3 3.0 v current limit indicator clind ? 0.3 vcc + 0.3 v interrupt indicator int ? 0.3 vcc + 0.3 v enable input en ? 0.3 5.5 v i 2 c communication lines sda, scl ? 0.3 vcc + 0.3 v compensation output comp ? 0.3 vcc + 0.3 v v1 power stage input voltage v1 ? 0.3 40 v positive current sense csp1 ? 0.3 40 v negative current sense csn1 ? 0.3 40 v positive current sense csp2 ? 0.3 40 v negative current sense csn2 ? 0.3 40 v feedback voltage fb ? 0.3 5.5 v
ncp81239 www.onsemi.com 5 table 2. maximum ratings over operating free ? air temperature range unless otherwise noted rating unit max min symbol cfet driver cfet ? 0.3 vcc + 0.3 v driver 1 and driver 2 positive rails bst1, bst2 ? 0.3 v wrt/pgnd ? 0.3 v wrt/vsw 35 v wrt/pgnd 5.5 v wrt/vsw v high side driver 1 and driver 2 hsg1, hsg2 ? 0.3 v wrt/pgnd ? 0.3 v wrt/vsw 30 v wrt/gnd 5.5 v wrt/vsw v switching nodes and return path of driver 1 and driver 2 vsw1, vsw2 ? 5.0 v 35 v v low side driver 1 and driver 2 lsg1, lsg2 ? 0.3 v 5.5 v pmosfet driver pdrv ? 0.3 40 v voltage differential agnd to pgnd ? 0.3 0.3 v csp1 ? csn1, csp2 ? csn2 differential voltage cs1dif, cs2dif ? 0.5 0.5 v pdrv maximum current pdrvi 0 10 ma maximum vcc current vcci 0 80 ma operating junction temperature range (note 1) tj ? 40 150 c operating ambient temperature range ta ? 40 85 c storage temperature range tstg ? 55 150 c thermal characteristics (note 2) qfn 32 5mm x 5mm maximum power dissipation @ ta = 25 c thermal resistance junction ? to ? air with solder pd r ja 3.53 35.4 w c/w lead temperature soldering (10 sec): reflow (smd styles only) pb ? free (note 3) rf 260 peak c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the maximum package power dissipation limit must not be exceeded. 2. the value of ja is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch fr ? 4 board with 1.5 oz. copper on the top and bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with t a = 25 c. 3. 60 ? 180 seconds minimum above 237 c. table 3. electrical characteristics (v1 = 12 v, v out = 1.0 v , t a = +25 c for typical value; ? 40 c < t a < 100 c for min/max values unless noted otherwise) parameter symbol test conditions min typ max units power supply v1 operating input voltage v1 4.5 28 v vdrv operating input voltage vdrv 4.5 5 5.5 v vcc uvlo rising threshold vcc start 4.16 v uvlo hysteresis for vcc vccv hys falling hysteresis 200 mv vdrv uvlo rising threshold vdrv start 4.16 v uvlo hysteresis for vdrv vdrv hys falling hysteresis 200 mv vcc output voltage vcc with no external load 4.90 5 v vcc drop out voltage vccdroop 30 ma load 150 mv vcc output current limit iout vcc vcc loaded to 4.3 v 80 97 ma 4. ensured by design. not production tested.
ncp81239 www.onsemi.com 6 table 3. electrical characteristics (v1 = 12 v, v out = 1.0 v , t a = +25 c for typical value; ? 40 c < t a < 100 c for min/max values unless noted otherwise) v1 quiescent current iv1q en = 5v 4.2v v1 28v lsg1, lsg2,hsg1,hsg2 are open comp = 0v (not switching) 11 18 ma v1 shutdown supply current ivcc_sd en = 0v 4.2v v1 32v 6.6 7.7 ma vdrive switching current buck iv1_sw en = 5, cgate = 2.2 nf, vsw = 0 v fsw = 600 khz, comp = 1 v 12 ma vdrive switching current boost iv1_sw en = 5, cgate = 2.2 nf, vsw = 0 v fsw = 600 khz, comp = 1 v 12 ma voltage output voltage output accuracy fb dac_target = 00110010 dac_target = 01111000 dac_target = 11001000 0.495 1.188 1.98 0.5 1.2 2.0 0.505 1.212 2.02 v voltage accuracy over temperature voutert pwm in ccm mode, ? 40 c < t a < 100 c vfb > 0.5 v 0.17 v < vfb < 0.5 v 0.1 v < vfb < 0.17 ? 1.0 ? 2.0 ? 3.3 1.0 1.8 3.0 % vouter t a = 25 c vfb > 0.5 v 0.17 v < vfb < 0.5 v ? 0.35 ? 1.0 0.35 1.2 % transconductance amplifier gain bandwidth product gbw 3db (note 4) 5.2 mhz transconductance gm1 default 500 s max output source current limit gmsoc 60 80 a max output sink current limit gmsic 60 80 a voltage ramp vramp 1.4 v internal bst diode forward voltage drop vfbot i f = 10 ma, t a = 25 c 0.42 0.46 0.51 v reverse bias leakage current dil bst ? vsw = 5 v v sw = 28 v, t a = 25 c 0.05 0.16 a bst ? vsw uvlo bst1 _uvlo rising, note 4 3.5 v bst ? vsw hysteresis bst _hys note 4 300 mv oscillator oscillator frequency fsw_0 fsw = 000, default 540 600 660 khz fsw_1 fsw = 001 135 150 166 khz fsw_7 fsw = 110 1058 1200 1320 khz oscillator frequency accuracy fswe ? 12 10 % minimum on time mot measured at 10% to 90% of vcc, ? 40 c < t a < 100 c 50 ns minimum off time moft measured at 90% to 10% of vcc, ? 40 c < t a < 100 c 90 ns int thresholds interrupt low voltage vinti iint(sink) = 2 ma 0.04 v interrupt high leakage current inii 3.3 v 3 11 na interrupt startup delay intpg soft start end to pg positive edge 2.1 ms 4. ensured by design. not production tested.
ncp81239 www.onsemi.com 7 table 3. electrical characteristics (v1 = 12 v, v out = 1.0 v , t a = +25 c for typical value; ? 40 c < t a < 100 c for min/max values unless noted otherwise) interrupt propagation delay pgi delay for power good in 3.3 ms pgo delay for power good out 100 ns power good threshold pgth power good in from high vprofile =0000 margin = 000 105 % pgth power good in from low vprofile = 0000 margin = 000 95 % pgthys pg falling hysteresis vprofile = 0000 margin = 000 2.5 % fb overvoltage threshold fb_ov vprofile = 0000 margin = 000 116 % overvoltage propagation delay vfb_ovdl 1 cycle external current sense (cs1,cs2) offset current measurement osi0 csp1 ? csn1 or csp2 ? csn2 = 0mv 110 na offset voltage measurement osvo cs = 0 a 40 v positive current measurement high cs10 csp1 ? csn1 or csp2 ? csn2 = 100 mv 500 a transconductance gain factor csgt current sense transconductance vsense = 1 mv to 100 mv 5 ms transconductance deviation csge ? 20 20 % current sense common mode range cscmmr 3 28 v ? 3db small signal bandwidth csbw vsense (ac) = 10 mvpp, rgain = 10 k (note 4) 30 mhz input sense voltage full scale isvfs 100 mv cs output voltage range csor vsense = 100 mv rset = 6k 0 3 v external current limit (clind) current limit indicator output low clindl input current = 500 a 5.6 10 mv current limit indicator output high clindh input current = 500 a 4.0 5.0 v internal current sense internal current sense gain for pwm icg cspx ? csnx = 100 mv 9.30 9.8 10.42 v/v positive peak current limit trip ppclt int_cl = 00, 34 39 44 mv negative valley current limit trip nvclt int_cl_neg = 00 31 40 45 mv switching mosfet drivers hsg1 hsg2 pullup resistance hsg_pu bst ? vsw = 4.5 v 2.8 hsg1 hsg2 pulldown resistance hsg_pd bst ? vsw = 4.5 v 1.2 lsg1 lsg2 pullup resistance lsg_pu lsg ? pgnd = 2.5 v 3.3 lsg1 lsg2 pulldown resistance lsg_pd lsg ? pgnd = 2.5 v 0.9 hsg falling to lsg rising delay hslsd 15 ns lsg falling to hsg rising delay lshsd 15 ns 4. ensured by design. not production tested.
ncp81239 www.onsemi.com 8 table 3. electrical characteristics (v1 = 12 v, v out = 1.0 v , t a = +25 c for typical value; ? 40 c < t a < 100 c for min/max values unless noted otherwise) cfet cfet drive voltage cfetdv vcc v source/sink current cfetss cfet clamped to 2 v 2 a pull down delay cfetd measured at 10% to 90% of vcc, ? 40 c < t a < 100 c 1.3 ms cfet pull down resistance cfetr measured with 1 ma pull up cur- rent, after 10ms rising edge delay 1.3 k slew rate/soft start charge slew rate slewp slew = 00, fb = 0.1 vout slew = 11, fb = 0.1 vout 0.6 4.8 mv/ s discharge slew rate slewn slew = 00, fb = 0.1 vout slew = 11, fb = 0.1 vout ? 0.6 ? 4.8 mv/ s prebias level pblv fb=0.1vout 300 mv dead battery/vconn dead battery input voltage range vdb 4.5 5 5.25 v dead battery output voltage vio vdb = 5 v, ? 40 c < t a < 100 c output current 32 ma 4.4 4.7 4.77 v dead battery current limit db_lim vdb = 5 v, v1 greater than 2 v 29 57 78 ma enable en high threshold voltage enht em_mask = enpu = enpol = 0 798 808 mv en low threshold voltage enlt 652 665 mv en pull up current ien_up en = 0 v 5 a en pull down current ien_dn en = vcc 5 a i 2 c interface voltage threshold i2cvth 0.95 1 1.05 v propagation delay i2cpd (note 4) 25 ns communication speed i2csp 0.400 1 mhz thermal shutdown thermal shutdown threshold tsd (note 4) 151 c thermal shutdown hysteresis tsdhys (note 4) 28 c pdrv pdrv operating range 0 28 v pdrv leakage current pdrv_ids fet off, vpdrv = 28 v 180 na pdrv saturation voltage pdrv_vds isnk = 10 ma 0.20 v 4. ensured by design. not production tested.
ncp81239 www.onsemi.com 9 application information dual edge current mode control when dual edge current mode control is used, two voltage ramps are generated that are 180 degrees out of phase. the inductor current signal is added to the ramps to incorporate current mode control. the first ramp, called the buck_ramp or 0_ramp, since it is the leading ramp and has no phase lag with gained current signal imposed on it, will generate the buck_pwm_comp signal. the second ramp, called the boost_ramp or 180_ramp, since it has a phase lag of 180 degrees with gained current signal imposed on it, will generate the boost_pwm_comp signal. the designer will note that the triangular wave shape of the ramps lend themselves to crossing twice at the midpoint of the boost_ramp ascension and buck_ramp dissention and vice versa. the point at which they intersect the midpoint of the ramp is the 100% duty cycle level for buck mode and the 0% duty cycle level for boost mode conversion. further, when the comp voltage is below the midpoint, the converter is in buck mode and when it is above the midpoint it is in boost mode. the example of the timing diagrams are shown in figure 4. when in buck mode, if the buck_pwm_comp is high and boost_pwm_comp is high s1 is on and s2 is off. likewise, when in buck mode, if the buck_pwm_comp is high and boost_pwm_comp is low, s1 is off and s2 is on. during buck mode, s3 is always off and s4 is always on. in boost mode if the buck_pwm_comp is low and boost_pwm_comp is high, s3 is on and s4 is off. likewise, when the buck_pwm_comp is low and boost_pwm_comp is low s3 is off and s4 is on. during boost mode s1 is always on and s2 is always off. figure 4. transitions for dual edge 4 switch buck boost boost ramp 180_ramp buck ramp 0_ramp boost pwm comp buck pwm comp s1 comp s2 s3 s4 v1 v2 l1 s1 s2 s4 s3
ncp81239 www.onsemi.com 10 feedback and output voltage profile the feedback of the converter output voltage is connected to the fb pin of the device through a resistor divider. internally fb is connected to the inverting input of the internal transconductance error amplifier. the non ? inverting input of the gm amplifier is connected to the internal reference. the internal reference voltage is by default 0.5 v. therefore a 10:1 resistor divider from the converter output to the fb will set the output voltage to 5v in default. the reference voltage can be adjusted with 10 mv(default) or 5 mv steps from 0.1 v to 2.55 v through the voltage profile register (01h), which makes the continuous output voltage profile possible through an external resistor divider. for example, by default, if the external resistor divider has a 10:1 ratio, the output voltage profile will be able to vary from 1 v to 25.5 v with 100 mv steps. table 4. voltage profile settings vps_7 vps_6 vps_5 vps_4 vps_3 vps_2 vps_1 vps_0 voltage profile hex value reference voltage (mv) 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 1 01h 10 0 0 0 0 0 0 1 0 02h 20 ? ? ? ? ? ? ? ? ? ? 0 0 1 1 0 0 1 0 32h 500 (default) ? ? ? ? ? ? ? ? ? ? 1 1 0 0 0 1 1 1 c7h 1990 1 1 0 0 1 0 0 0 c8h 2000 1 1 1 1 1 1 1 1 ffh 2550 transconductance voltage error amplifier to maintain loop stability under a large change in capacitance, the ncp81239 can change the gm of the internal transconductance error amplifier from 87 s to 1000 s allowing the dc gain of the system to be increased more than a decade triggered by the adding and removal of the bulk capacitance or in response to another user input. the default transconductance is 500 s. table 5. available transconductance setting amp_2 amp_1 amp_0 amplifier gm value ( s) max ( s) min ( s) 0 0 0 87 95.7 78.3 0 0 1 100 110 90 0 1 0 117 128.7 105.3 0 1 1 333 366.3 299.7 1 0 0 400 440 360 1 0 1 500 550 450 1 1 0 667 733.7 600.3 1 1 1 1000 1100 900 programmable slew rate the slew rate of the ncp81239 is controlled via the i 2 c registers with the default slew rate set to 0.6 mv/ s (fb = 0.1 v2, assume the resistor divider ratio is 10:1) which is the slowest allowable rate change. the slew rate is used when the output voltage starts from 0 v to a user selected profile level, changing from one profile to another, or when the output voltage is dynamically changed. the output voltage is divided by a factor of the external resistor divider and connected to fb pin. the 9 bit dac is used to increase the reference voltage in 10 or 5 mv increments. the slew rate is decreased by using a slower clock that results in a longer time between voltage steps, and conversely increases by using a faster clock. the step monotonicity depends on the bandwidth of the converter where a low bandwidth will result in a slower slew rate than the selected value. the available slew rates are shown in table 6. the selected slew rate is maintained unless the current limit is tripped; in which case the increased voltage will be governed by the positive current limit until the output voltage falls or the fault is cleared.
ncp81239 www.onsemi.com 11 figure 5. slew rate limiting block diagram and waveforms 9 bit dac + ? v2 fb = 0.1*v2 dac_traget cc rc dac_traget_lsb vref 2.56 v ci table 6. slew rate selection slew bits soft start or voltage transition (fb = 0.1*v2) slew_0 0.61 mv/ s slew_1 1.2 mv/ s slew_2 2.4 mv/ s slew_3 4.9 mv/ s the discharge slew rate is accomplished in much the same way as the charging except the reference voltage is decreased rather than increased. the slew rate is maintained unless the negative current limit is reached. if the negative current limit is reached, the output voltage is decreased at the maximum rate allowed by the current limit (see the negative current limit section). soft start during a 0 v soft start, standard converters can start in synchronous mode and have a monotonic rising of output voltage. if a prebias exists on the output and the converter starts in synchronous mode, the prebias voltage could be discharged. the ncp81239 controller ensures that if a prebias is detected, the soft start is completed in a non ? synchronous mode to prevent the output from discharging. during softstart, the output rising slew rate will follow the slew rate register with default value set to 0.6 mv/ s (fb = 0.1*v2). frequency programming the switching frequency of the ncp81239 can be programmed from 150 khz to 1.2 mhz via the i 2 c interface. the default switching frequency is set to 600 khz. once the part is enabled, the frequency is set and cannot be changed while the part remains enabled. the part must be disabled with no switching prior to writing the frequency bits into the appropriate i 2 c register. table 7. frequency programming table name bit definition description freq1 03h [2:0] frequency setting 3 bits that control the switching frequency from 150 khz to 1 mhz. 000: 600 khz 001: 150 khz 010: 300 khz 011: 450 khz 100: 750 khz 101: 900 khz 110: 1.2 mhz 111: reserved current sense amplifiers internal precision differential amplifiers measure the potential between the terminal csp1 and csn1 or csp2 and csn2. current flows from the input v1 to the output in a buck boost design. current flowing from v1 through the switches to the inductor passes through r sense . the external sense resistor, r sense , has a significant effect on the function of current sensing and limiting systems and must be chosen with care. first, the power dissipation in the resistor should be considered. the system load current will cause both heat and voltage loss in r sense . the power loss and voltage drop drive the designer to make the sense resistor as small as possible while still providing the input dynamic range required by the measurement. note that input dynamic range is the dif ference between the maximum input
ncp81239 www.onsemi.com 12 signal and the minimum accurately measured signal, and is limited primarily by input dc offset of the internal amplifier. in addition, r sense must be small enough that v sense does not exceed the maximum input voltage 100 mv, even under peak load conditions. the potential difference between cspx and csnx is level shifted from the high voltage domain to the low voltage vcc domain where the signal is split into two paths. the first path, or external path, allows the end user to observe the analog or digital output of the high side current sense. the external path gain is set by the end user allowing the designer to control the observable voltage level. the voltage at cs1 or cs2 can be converted to 8 bits by the adc and stored in the internal registers which are accessed through the i 2 c interface. the second path, or internal path, has internally set gain of 10 and allows cycle by cycle precise limiting of positive and negative peak input current limits. figure 6. block diagram and typical connection for current sense r cs iload rsense 5 m + ? + ? + ? + ? csn1/csn2 csp1/csp2 c cs cs2 clind vcm + ? 10x + ? + ? positive current limit negative current limit clip clin vcc internal path cs1 or cs2 adc r cs1 c cs cs1 + ? + ? cs2 mux cs1 mux 2 2 ramp 1 ramp 2 10x(csp2-csn2) 10x(csp1-csn1) positive current limit internal path the ncp81239 has a pulse by pulse current limiting function activated when a positive current limit triggers. csp1/csn1 will be the positive current limit sense channel. when a positive current limit is triggered, the current pulse is truncated. in both buck mode and in boost mode the s1 switch is turned off to limit the energy during an over current event. the current limit is reset every switching cycle and waits for the next positive current limit trigger. in this way, current is limited on a pulse by pulse basis. pulse by pulse current limiting is advantageous for limiting energy into a load in over current situations but are not up to the task of limiting energy into a low impedance short. to address the low impedance short, the ncp81239 does pulse by pulse current limiting for 2 ms known as ilim timeout or until the output voltage falls below 300 mv, the controller will enter into fast stop. the ncp81239 remains in fast stop state with all switches driven off for 10 ms. once the 10 ms has expired, the part is allowed to soft start to the previously programmed voltage and current level if the short circuit condition is cleared. the internal current limits can be controlled via the i 2 c interface both in trip level and in function. the internal positive and negative current limit can be masked such that they do not activate when they are exceeded; they will not trigger system protection as shown in table 8. table 8. internal peak current limit clin_1 clin_0 clim delta value (mv) csp2 ? csn2 (mv) current at rsense = 5 m (a) 0 0 ? 400 ? 40 (default) ? 8 0 1 ? 250 ? 25 ? 5 1 0 ? 150 ? 15 ? 3
ncp81239 www.onsemi.com 13 table 8. internal peak current limit 1 1 0 0 0 clip_1 clip_0 clim delta value (mv) csp1 ? csn1 (mv) current at rsense = 5 m (a) 0 0 380 38 (default) 7.6 0 1 230 23 4.6 1 0 110 11 2.2 1 1 700 70 14 table 9. internal peak current limit int_c l1 int_c l0 internal current limit positive negative 0 0 on on 0 1 on off 1 0 off on 1 1 off off negative current limit internal path negative current limit can be activated in a few instances, including light load synchronous operation, heavy load to light load transition, output overvoltage, and high output voltage to lower output voltage transitions. csp2/csn2 will be the negative current limit sense channel. during light load synchronous operation, or heavy load to light load transitions the negative current limit can be triggered during normal operation. when the sensed current exceeds the negative current limit, the s4 switch is shut off preventing the discharge of the output voltage both in buck mode and in boost mode if the output is in the power good range. both in boost mode and in buck mode when a negative current is sensed, the s4 switch is turned off for the remainder of either the s4 or s2 switching cycle and is turned on again at the appropriate time. in buck mode, s4 is turned off at the negative current limit transition and turned on again as soon as the s2 on switch cycle ends. in boost mode, the s4 switch is the rectifying switch and upon negative current limit the switch will shut off for the remainder of its switching cycle. external path (cs1, cs2, clind) the voltage drop across the sense resistors as a result of the load can be observed on the cs1 and cs2 pins. the voltage drop is converted into a current by a transconductance amplifier with a typical gm of 5 ms. the final gain of the output is determined by the end users selection of the r cs resistors. the output voltage of the cs pin can be calculated from equation 1. the user must be careful to keep the dynamic range below 3.0 v when considering the maximum short circuit current. v cs (i load_max *r sense * trans) * r cs (eq. 1) 2.967 v (8.5 a * 5 m * 5 ms) * 13.96 k r cs v cs i load *r sense * trans 13.96 k 2.967 v 8.5 a * 5 m *5ms the speed and accuracy of the dual amplifier stage allows the reconstruction of the input and output current signal, creating the ability to limit the peak current. if the user would like to limit the mean dc current of the switch, a capacitor can be placed in parallel with the r cs resistors. the external cs voltages are connected to 2 high speed low offset comparators. the comparators output can be used to suspend operation until reset or restart of the part depending on i 2 c configuration. when one of the comparators trips if not masked, the external clind flag is triggered to indicate that the internal comparator has exceeded the preset limit. the default comparator setting is 250 mv which is a limit of 500 ma with a current sense resistor of 5 m and an r cs resistor of 20 k . the block diagram in shows the programmable comparators and the settings are shown in table 10. table 10. register setting for the clim comparators climx_1 climx_0 csx_lim (v) current at rsense = 5 m rset = 20 k (a) current at rsense = 5 m rset = 10 k (a) 0 0 0.25 .5 1 0 1 0.75 1.5 3 1 0 1.5 3 6 1 1 2.5 5 10
ncp81239 www.onsemi.com 14 overvoltage protection (ovp) when the divided output voltage is 115% (typical) above the internal reference voltage for greater than one switching cycle, an ov fault is set. during an overvoltage fault, s1 is driven off, s2 is driven on, and s3 and s4 are modulated to discharge the output voltage while preventing the inductor current from going beyond the i 2 c programmed negative current limit. figure 7. diagram for ov protection v1 v2 l1 s1 s2 s4 s3 during overvoltage fault detection the switching frequency changes from its i 2 c set value to 50 khz to reduce the power dissipation in the switches and prevent the inductor from saturating. oov is disabled during voltage changes to ensure voltage changes and glitches during slewing are not falsely reported as faults. the oov faults are reengaged 1 ms after completion of the soft start. figure 8. ov block diagram ? + vfb ov_ref ov ov_msk table 11. overvoltage masking ov_mak description 0 ov action and indication unmasked 1 ov action and indication masked power good monitor (pg) ncp81239 provides two window comparators to monitor the internal feedback voltage. the target voltage window is 5% of the reference voltage (typical). once the feedback voltage is within the power good window, a power good indication is asserted once a 3.3 ms timer has expired. if the feedback voltage falls outside a 7% window for greater than 1 switching cycle, the power good register is reset. power good is indicated on the int pin if the i 2 c register is set to display the pg state. during startup, int is set until the feedback voltage is within the specified range for 3.3 ms. figure 9. pg block diagram ? + vfb pg_low pg_high ? + pg pg_msk table 12. power good masking pg_msk description 0 pg action and indication unmasked 1 pg action and indication masked thermal shutdown the ncp81239 protects itself from overheating with an internal thermal shutdown circuit. if the junction temperature exceeds the thermal shutdown threshold (typically 150 c), all mosfets will be driven to the off state, and the part will wait until the temperature decreases to an acceptable level. the fault will be reported to the fault register and the int flag will be set unless it is masked. when the junction temperature drops below 125 c (typical), the part will discharge the output voltage to vsafe 0 v. if a thermal fault is triggered during the discharge, the part will again be halted until the thermal fault is cleared. the discharging of the output will continue until it is less than 300 mv; at which time it is deemed to be vsafe 0 v and can be reconfigured to usb 2.0, a benign state of operation. table 13. thermal trip not available for customers thermtrip definition 0 thermal trip performs as designed 1 thermal trip is masked and will not shut the part off cfet turn on the cfet is used to engage the output bulk capacitance after successful negotiations between a consumer and a provider. the usb power delivery specification requires that no more than 30 f of capacitance be present on the vbus rail when sinking power. once the consumer and provider have completed a power role swap, a larger capacitance can be added to the output rail to accommodate a higher power level. the bulk capacitance must be added in such a way as to minimize current draw and reduce the
ncp81239 www.onsemi.com 15 voltage perturbation of the bus voltage. the ncp81239 incorporates a right drive circuit that regulates current into the gate of the mosfet such that the mosfet turns on slowly reducing the drain to source resistance gradually. once the transition from high to low has occurred in a controlled way, a strong pulldown driver is used to ensure normal operation does not turn on the power n ? mosfet engaging the bulk capacitance. the cfet must be activated through the i 2 c interface where it can be engaged and disengaged. the default state is to have the cfet disengaged. figure 10. cfet drive cfet 30 f c bulk vcc cfet 10 ms rising edege delay vbus lsg2 hsg2 q cfet table 14. cfet activation table cfet_0 description 0 cfet drive pulldown 1 cfet drive pull up pfet drive the pmos drive is an open drain output used to control the turn on and turn off of pmosfet switches at a floating potential. the external pmos can be used as a cutoff switch, enable for an auxiliary power supply, or a bypass switch for a power supply. the rdson of the pulldown nmosfet is typically 20 allowing the user to quickly turn on large pmosfet power channels. figure 11. pfet drive pdrv pfet_drv vbus table 15. pfet activation table pfet_drv description 0 nfet off (default) 1 nfet on
ncp81239 www.onsemi.com 16 analog to digital converter the analog to digital converter is a 7 ? bit a/d which can be used as an event recorder, an input voltage sampler, output voltage sampler, input current sampler, or output current sampler. the converter digitizes real time data during the sample period. the internal precision reference is used to provide the full range voltage; in the case of csp1(input voltage), or fb (with 10:1 external resistor divider) the full range is 0 v to 25.6 v. the csp1 is internally divided down by 10 before it is digitized by the adc, thus the range of the measurement is 0 v ? 2.56 v, same as fb. the resolution of the csp1 and fb voltage is 20 mv at the analog mux, but since the voltage is divided by 10 output voltage resolution will be 200 mv. when cs1 and cs2 are sampled, the range is 0 v ? 2.56 v. the resolution will be 20 mv in the cs monitoring case. the actual current can be calculated by dividing the cs1 or cs2 values with the factor of rsense*5ms*rcsx, the total gain from the current input to the external current monitoring outputs. figure 12. analog to digital converter table 16. adc byte msb 5 4 3 2 1 lsb data d6 d5 d4 d3 d2 d1 d0 table 17. register setting for enabling desired adc behaviour adc_2 adc_1 adc_0 description 0 0 0 poll amux inputs on interrupt fault state control, a/d enabled, data convert all settings in interrupt 0 0 1 sets amux to cs1, reads once 0 1 0 sets amux to cs2, reads once 0 1 1 sets amux to v1, reads once 1 0 0 sets amux to fb (fb voltage), reads once 1 0 1 disable a/d conversion low power 1 1 0 poll amux inputs one at a time continuously 1 1 1 spare
ncp81239 www.onsemi.com 17 table 18. register setting for adc flag clear behaviour adc_flag description 0 flag cleared, indicating that the required polling has not yet completed. 1 flag set, indicating that the required polling has been completed; this is not set when continuous polling is used. once a read is completed, the flag is reset. interrupt control the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected. individual bits generating interrupts will be set to 1 in the intack register (i 2 c read only registers), indicating the interrupt source. intack register is automatically reset by an i 2 c read. all interrupt sources can be masked by writing 1 in register intmsk. masked sources will never generate an interrupt request on the int pin. the int pin is an open drain output. a non ? masked interrupt request will result in the int pin being driven high. when the host reads the intack registers, the int pin will be driven low and the interrupt register intack is cleared. figure 13 illustrates the interrupt process. figure 13. interrupt logic ov ov ov_int temp temp_int pg pg_int intocp intocp _int intack intack_int extoc extoc_int vchn vchn_int shutdn shutdn_int temp int ov_reg temp_reg intack table 19. interpretation table interrupt name description ov output over voltage shutdown shutdown detection (en=low) temp ic thermal trip pg power good trip thresholds exceeded intocp internal current limit trip extoc external current trip from clind vchn output negative voltage change intack i2c ack signal to the host i 2 c address ncp81239 has four address selectable factory settings (add0 to add3). different address settings can be generated upon request to on semiconductor. the default address is set to e8h /e9h.
ncp81239 www.onsemi.com 18 table 20. i 2 c address i 2 c address hex a7 a6 a5 a4 a3 a2 a1 a0 add0 (default) w 0xe8 r 0xe9 1 1 1 0 1 0 0 r/w add1 w 0xea r 0xeb 1 1 1 0 1 0 1 r/w add2 w 0xec r 0xed 1 1 1 0 1 1 0 r/w add3 w 0xee r 0xef 1 1 1 0 1 1 1 r/w
ncp81239 www.onsemi.com 19 package outline qfn32 5x5, 0.5p case 485ce issue o seating note 4 k 0.15 c (a3) a a1 d2 b 1 17 32 e2 32x 8 24 l 32x bottom view top view side view d a b e 0.15 c pin one reference 0.10 c 0.08 c c 25 e notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.20 0.30 d 5.00 bsc d2 3.40 3.60 e 5.00 bsc e2 e 0.50 bsc l 0.30 0.50 3.40 3.60 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.70 0.30 3.70 32x 0.62 32x 5.30 5.30 note 3 dimensions: millimeters l1 detail a l alternate constructions l ??? ??? a-b m 0.10 b c m 0.05 c k 0.20 ??? l1 ??? 0.15 pitch recommended on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp81239/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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